In WP02 algorithm/architecture co-design of platform components is covered. To achieve the energy efficiency, high computing load and hard real-time constraints, reconfigurable architecture must be designed very close to the detailed application requirements. Similarly, algorithmic solutions must take into account the architecture details to guarantee the most efficient execution. Consequently, algorithm and architecture design must ideally be conducted jointly. Recently emerging Electronic System-Level (ESL) design methodologies makes such approach possible. In WP02, the ESL approach will be applied to the algorithm and architecture design of key component of the Multi-Base reconfigurable baseband platform. Components that reveal to be bottleneck in achieving the aforementioned constraints will be specifically targeted. These will be identified from work in WP01 (components supporting forward error correction and/or full-spectrum scanning have high probability to be bottleneck). To further enhance the energy-efficiency (at system-level), WP02 will capitalise of the “performance/complexity scalable design paradigm” where both algorithm and architecture are designed so that the ensemble exposes a controllable trade-off between functional performance and computation load and efficiency. So that the ensemble can be most effectively adapted, at run-time, to the variable user and environment requirements.
The resulting scalable architecture will be further implemented in WP04. Scalable algorithms will then be mapped to the architecture implementation as software entities. WP02 will also contribute to the proof of the aforementioned concept within WP05.

 

WP03 – Platform framework:

Multiple mode radio terminals have been essential in most people’s daily life and several new radio systems are introduced to our daily life per year. Costs to integrate multiple baseband hardware modules are too high and the time to market is too long. Programmable solutions will therefore be the dominant choice in the future to achieve sufficient flexibility and to minimise the time to market.
To meet both performance and low power low silicon costs, heterogeneous (multi core) architecture is essential for different classes of radio codec algorithms. However, it is difficult to integrate and use heterogeneous cores. Integration platform is therefore required. Costs of a general OCN (on chip connection network) are too high for radio baseband of a terminal product. Therefore, a dedicated radio baseband platform with minimised silicon cost, power consumption, latency, and enough bandwidth will be essential for portable and battery driven terminals.

The platform will be the integrator to radio baseband system designer (WP01). It will be used to collect function modules (WP02), it will regulate the design of module interfaces (WP04), it will provide communications between modules (WP02), and it will provide simulation on radio baseband subsystem level (WP01). Finally, it will be the behaviour model of radio baseband subsystem as a functional component in the radio system (WP01).

 

WP04 – Implementation of the functional platform:

For the system envisioned within the project we see that the processing capability of the hardware architecture has to be far higher than it is today. This comes both from the increase in algorithm  omplexity in future systems and the aggregated computational demands by simultaneous transmission and reception of different standards. Examples from within baseband technology are new FEC structures and multiple antenna systems. At the same time the flexibility of the hardware platform has to be increased for a variety of reasons, e.g.

•  Multi-standard functionality,

•  Reusability for a wider range of products and

•  Adaptation to varying channel conditions.

This has to be performed with the requirements on ever decreasing energy consumption. Furthermore, with technology scaling towards smaller technology nodes we see a paradigm shifts in the power consumption profile with a larger and larger part of the power being related to static power. Therefore, it is crucial to have a close relation to advances in silicon technology when future architectures are considered. From a baseband hardware perspective those issues have to be dealt with both on the overall processing architecture and on the development of key building blocks for hardware acceleration of especially demanding algorithmic primitives.

 

WP05 – Proof of concept:

The goal of the WP05 is to prove in silicon that the requirements on the building blocks for the reconfigurable radio baseband processor in a multi frequency-band and multi access phone can be met with designs in sub micron CMOS technologies. Depending on availability and stability of multi project shuttles, the tape out in 45nm or 32nm CMOS is planned at the beginning of the third year of the project. The planned metal re-spin will allow bug-fixing and corrective actions in design and architecture. Infineon will provide access to multi project shuttles for the partners depending on availability and stability of the respective technologies. The silicon will be packaged in WLB packages to support extensive measurements and the use in demonstrators.

It is planned to give the partners the required access and support to the Infineon design environment (process design kit, tools, library, etc). The partners will tape out their blocks individually. Tape-out post-processing, mask generation and front-end manufacturing will be done at an Infineon facility or at an Infineon foundry. 
The silicon test-chips will be fully evaluated and characterised by the respective partners in their labs.

 

WP06 – Project management, Dissemination and Standardisation:

WP06 is dedicated to management, dissemination and standardisation.